To realize a nonvolatile memory device capable of storing multiple values in a nonvolatile memory cell, hitherto, it has been proposed to provide a nonvolatile memory cell with plural states. That is, the electric charge injected in the floating gate is controlled in gradual steps and the threshold voltage of the nonvolatile memory cell is changed in gradual steps so that multiple values can be stored.
For example, when the writing charge is adjusted in four steps, two bits of data can be stored in each memory cell. In this case, as shown below, the data is written in at least two steps of applying writing voltage.
In the first step, a first voltage is applied to a memory cell in an erased state, and an electric charge is injected into the floating gate as the first step charge. In the second step, depending on the data to be stored, charges are injected into each memory cell by applying a second voltage or a third voltage higher than the second voltage in order to achieve a second step charge or a third step charge larger than the second step charge. As a result, the nonvolatile memory cell holds three writing states having different threshold voltages depending on the injected charge amount. With the addition of an erased state, two-bit data of four states may be stored. When reading out the data, differences in reading current amounts is detected depending on differences in threshold voltages of the nonvolatile memory cell.
In Japanese unexamined patent publication No. 2001-156275 (hereinafter referred to as Patent Document 1), as shown in FIG. 25, a memory transistor Trmc has a gate insulating film 120 including discrete traps and a control gate electrode 170. Switch transistors Trsw having switch gate electrodes 160-1, 160-2 are provided at both sides, and diffusion layers 140-1, 140-2 connected to source lines/bit lines are formed at the outer side. By writing locally into the gate insulating film 120, one memory cell operates as a multi-storage device, accumulating information of at least two bits.
The electric charge captured in the gate insulating film including discrete traps can hardly be moved in the horizontal direction on the substrate surface from the initially captured position. At present, a silicon nitride film, and a gate insulating film including fine particles of silicon nitride are known materials for the gate insulating film including discrete traps.
The writing operation is performed by injection from the source side. When the carrier passes the closed channel of either switch transistor Trsw, it is accelerated and energy is enhanced, while the carrier jumping into the channel of the memory transistor Trmc feels a high bias in the direction of control gate electrode 170 and is discretely captured in traps. Charges are accumulated with a certain distribution in the source region of the memory transistor Trmc. By conduction of the channels beneath the switch gate electrodes 160-1, 160-2 provided at both sides of the memory transistor Trmc, charges are accumulated at both sides of the gate insulating film 120 and two-bit data is stored.
In order to inject from the source side, the writing operation is conducted at the source side. The reading channel current may also be in the same direction.
In Japanese unexamined patent publication No. 2003-282741 (hereinafter referred to as patent document 2), as shown in FIG. 26, gate insulating films (SiO2 films) 250, 260 are formed on a silicon (Si) substrate 210, a pair of floating gates 270a, 270b are formed on the silicon oxide film 260, an ONO film 280 is formed to cover the floating gate 270 and silicon oxide films 250, 260, and a control gate 290 is formed as a word line on the ONO film 280. The pair of floating gates 270a, 270b are disposed independently on a source 230 and a drain 240 so that electrons from the source 230 and drain 240 can be individually injected and extracted. The floating gates 270a, 270b are side walls formed on a side wall of an insulating film which is later removed.
During the writing operation, electrons advancing in the channel from the source 230 toward the drain 240 gain a high energy near the drain 240 and become hot electrons, partly jumping over the silicon oxide film 260 to be injected into the floating gate 270b. Injection into the floating gate 270b can also be performed by inverting the bias relation of the source 230 and drain 240.
During the reading operation, while there is no electrons in the floating gates 270a, 270b, the channel is linked, and a current flows between the source 230 and drain 240, and data “1” is read out. While electrons are injected, the channel is cut off, and current does not flow between the source 230 and drain 240, and data “0” is read out. Thus, by writing, erasing, and reading out independently in the pair of floating gates 270a, 270b respectively, the storage capacity can be doubled.